The Widening Gap: Why TSMC Can’t Keep Up With the Hyperscaler Capex Arms Race

When Amazon announced $200 billion in 2026 capital expenditure guidance on its Q4 2025 earnings call last night, I did what any former buy-sider would do: I opened Daloopa and started pulling comps. Not against other hyperscalers but against the company that actually makes the silicon all that money is chasing- TSMC.

The result was striking. In 2015, the Big 4 hyperscalers (Amazon, Alphabet, Microsoft, and Meta) collectively spent about 3x what TSMC spent on capex. By 2026, that ratio will balloon to nearly 12x. The world’s most important chipmaker is being outspent by its own customers at a pace that is accelerating every quarter and TSMC’s CEO is openly telling you he’s nervous about it.

The Numbers Tell the Story

Using Daloopa, I pulled capex (i.e. PPE) from the cash flow statements of all five companies going back to 2015. For Microsoft, whose fiscal year ends in June, I aggregated quarterly filings into calendar years to create an apples-to-apples comparison.

2026E sources: AMZN $200B (Q4’25 earnings guidance, Feb 6 2026), GOOGL $180B midpoint ($175–185B guidance), MSFT $119.5B (annualized from $29.9B Q4 CY2025), META $125B midpoint ($115–135B guidance incl. finance leases), TSMC $54B midpoint ($52–56B guidance).

Read that last line again. Amazon alone will spend nearly 4x what TSMC plans to spend in 2026. The Big 4 combined will outspend the world’s most critical semiconductor manufacturer by almost 12-to-1.

“I’m Also Very Nervous About It”

What makes this divergence so fascinating is that TSMC’s CEO, C.C. Wei, is essentially telling the market he’s choosing not to match the pace. On TSMC’s Q4 2025 earnings call in January, Wei was remarkably candid when an analyst pressed him on whether AI demand was real:

This is the CEO of a company with 95%+ market share in advanced AI chip manufacturing, telling you he’s scared to spend $54 billion. Meanwhile, his customers are collectively deploying $624 billion without blinking.

Wei went on to describe his due diligence process — spending months personally calling cloud service providers to verify their demand signals:

Even after satisfying himself that demand is real, Wei emphasized discipline over aggression. On the same call, he stated TSMC would “remain disciplined in our capacity planning approach”, a phrase that would sound prudent in any other context, but takes on a different meaning when your four largest customers are telling you they need more chips than you can physically produce.

The CoWoS Bottleneck: Where the Rubber Meets the Road

The gap between hyperscaler demand and TSMC’s willingness to supply isn’t just theoretical. It’s playing out in real time through TSMC’s advanced packaging technology, CoWoS (Chip-on-Wafer-on-Substrate), which is essential for assembling multi-die AI accelerators that power every data center being built today.

On TSMC’s Q1 2025 call, Wei described CoWoS demand as:

By Q3, he was still working to “narrow the gap between the demand and supply,” acknowledging that “everything related, like frontend and backend capacity, is very tight.”

Even with TSMC doubling its CoWoS capacity in both 2024 and 2025 and planning to increase monthly output from around 80,000 wafers to as many as 130,000 by the end of 2026, it remains fully booked. NVIDIA alone reportedly secures over 60% of CoWoS capacity, leaving AMD, Google, Amazon, and all other custom ASIC designers competing for the rest. The shortage is so critical that second-tier chip designers have started exploring Intel’s EMIB and Foveros packaging as alternatives, not because they are better, but because CoWoS capacity simply isn’t available.

Why TSMC Won’t Just “Spend More”

There’s a structural reason TSMC can’t or won’t close this gap, and it comes down to the economics of semiconductor manufacturing versus everything else that goes into a data center.

Each dollar TSMC spends goes toward the most capital-intensive, technically complex manufacturing on Earth. Building a single leading-edge fab costs $20 billion or more. The tools alone, particularly ASML’s EUV lithography machines at roughly $380 million each, take years to procure and install. As TSMC’s CFO Wendell Huang noted on the Q4 call, “the capex dollar required to build 1,000 wafers per month of N2 (2nm) capacity is substantially higher than for N3 (3nm).” Each new node is more expensive than the last, with equipment intensity per wafer rising 30–50%.

Meanwhile, hyperscaler capex is increasingly going to everything except chips: land acquisition, building construction, power infrastructure (including nuclear restarts), cooling systems, networking equipment, and electrical grid connections. These are categories where spending can scale much faster than semiconductor fabrication. You can break ground on a new data center campus in months; a new fab takes three to five years from groundbreaking to volume production.

The implication is that TSMC’s share of the total AI infrastructure spend stack is structurally declining. In the 2015–2023 era, TSMC captured roughly 20–25% of the Big 4’s combined capex, suggesting chips were a meaningful share of total infrastructure cost. By 2026, TSMC captures less than 9%. The semiconductor layer is becoming a smaller slice of a much larger pie.

What This Means for Investors

This widening ratio creates several dynamics worth watching.

First, TSMC’s pricing power is immense and increasing. As the sole provider of a critical input with capacity fully booked years in advance, they set the price. Prices for advanced packaging are rising 10–20% annually, and leading-edge wafer prices are following suit. TSMC’s gross margin reached 62.3% in Q4 2025 — a remarkable figure for a capital-intensive manufacturer.

Second, hyperscalers’ capex trajectory may be less about chips and more about other factors. When Amazon guides to $200 billion in capex, much of that is real estate, power, and construction — categories where returns are measured in decades, not quarters. The semiconductor bill, while enormous in absolute terms, is becoming a smaller percentage of the total investment.

Third, the capacity constraint acts as a natural limit on AI expansion. No matter how much money hyperscalers invest in infrastructure, the speed of AI deployment is ultimately limited by how many advanced chips TSMC can produce and package. Wei’s nervousness serves as the market’s safety valve — a disciplined manufacturer unwilling to overbuild helps prevent a repeat of the telecom bubble’s disastrous overcapacity.

As Wei put it:

That’s the tension at the heart of the AI infrastructure boom: limitless demand meeting deliberately constrained supply, with the ratio between them widening every quarter.